Competing ultrafast photoinduced electron transfer and intersystem crossing of [Re(CO)(3)(Dmp)(His124)(Trp122)]+ in Pseudomonas aeruginosa azurin:a nonadiabatic dynamics study

We present a computational study of sub-picosecond nonadiabatic dynamics in a rhenium complex coupled electronically to a tryptophan (Trp) side chain of Pseudomonas aeruginosa azurin, a prototypical protein used in the study of electron transfer in proteins. To gain a comprehensive understanding of the photoinduced processes in this system, we have carried out vertical excitation calculations at the TDDFT level of theory as well as nonadiabatic dynamics simulations using the surface hopping including arbitrary couplings (SHARC) method coupled to potential energy surfaces represented with a linear vibronic coupling model. The results show that the initial photoexcitation populates both singlet metal-to-ligand charge transfer (MLCT) and singlet charge-separated (CS) states, where in the latter an electron was transferred from the Trp amino acid to the complex. Subsequently, a complex mechanism of simultaneous intersystem crossing and electron transfer leads to the sub-picosecond population of triplet MLCT and triplet CS states. These results confirm the assignment of the sub-ps time constants of previous experimental studies and constitute the first computational evidence for the ultrafast formation of the charge-separated states in Re-sensitized azurin

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

We present a low-power, energy efficient 32-bit RISC-V microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures, by using an adaptive reverse body biasing aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from -40 {\deg}C to 125 {\deg}C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode.Comment: accepted at ISOCC 202

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications

Evaluierung der Eignung von High-Level Designmethodik zur Entwicklung digitaler Signalverarbeitung für Hochge-schwindigkeitsanwendungen

Die Datenraten moderner drahtloser Kommunikationssysteme nehmen von Generation zu Generation zu. Ein Ansatz diesen Anforderungen gerecht zu werden, ist die Verarbeitungsgeschwindigkeit und damit Taktfrequenz dieser Systeme zu erhöhen. Durch eine steigende Komplexität moderner Kommunikationssysteme, wird deren Entwicklung immer zeitaufwendiger und kostenintensiver. Die moderne C-basierte High-Level Synthese bietet eine Möglichkeit die Entwicklungszeit deutlich zu verringern. Ziel dieser Arbeit ist es, die Eignung des High-Level Synthese-Ansatzes für Hochgeschwindigkeitssignalverarbeitung zu untersuchen

‘Priest’—‘Eparchy-arch’—‘Speaker of the ethnos’

In the Roman Eastern provinces, the concept and rituals of a province-wide imperial cult were based on a pre-existing tradition of Hellenistic ruler’s divinization and worship. But its formal mise en place was conformed to the new territorial framework of Roman administration: a gubernatorial provincia/ἐπαρχεία appears subdivided into several administrative sub-provinces that were likewise called provinciae/ἐπαρχεῖαι. The cities of almost all known eparchies in terms of sub-provinces formed koina responsible for the provincial imperial cult and the political representation of the provincials headed by priestly officials, such as bithyniarchai or ‘(high-)priests of the eparchy/-ies’, whose titles refer explicitly to the represented sub-province. The correlation between these koina and Roman territorial administration from almost all Eastern provinces demands more political functions of the koinon-officials than only priestly ones, as shown by the frequently combined titulatures